1. Field of the Invention
The present invention relates to a method of evaluating a semiconductor device, and particularly to an evaluating method of a semiconductor device, which evaluates an impurity profile of an ESD (Electric Static Discharge) protective element.
2. Description of the Related Art
In general, an ESD protective element 51 is inserted between an input electrode 52 or an output electrode 53 and an internal circuit 50 in a semiconductor device in such a manner that when an ESD surge is applied from the input electrode 52 or the output electrode 53 as shown in an input circuit (FIG. 6(a)) and an output circuit (FIG. 6(b)), an excessive current does not flow through the internal circuit 50.
When the voltage applied to the internal circuit or the current that flows through the internal circuit exceeds the rating, such a protective element is designed in such a manner that the current flows through the ESD protective element in a moment. Since elements contained in the ESD protective device and the internal circuit are fabricated in a similar process only for the protective element and so as not to increase the number of processes, impurity profiles of respective impurity layers constituting the protective element are identical to a layer constituting the internal circuit.
While a MOSFET, a PN diode or an SCR (Silicon Controlled Rectifier) is being used as the ESD protective element, the SCR among them has been widely used because it is small in hold voltage and low in on resistance. The small hold voltage makes it possible to reduce power consumption defined by the current x voltage, and the low on resistance allows the current to flow in the ESD protective element in a moment, thereby bringing about an effect that ESD resistance can be enhanced.
FIG. 7(a) is an explanatory diagram showing a schematic structure of a general SCR 60. A current flows from an anode 61 to a cathode 62 through a PD layer, an NW layer, a PW layer and an ND layer. A P+ layer and an N+ layer are respectively formed in the PD layer and the ND layer for the purpose of a reduction in resistance, and the NW layer is connected to the anode to control the current.
Although the SCR is accompanied by the drawback that a turn-on voltage (voltage at which the current starts to flow) is high, an LVTSCR (Low Voltage Triggering SCR) shown in FIG. 7(b) has been proposed and widely used to reduce the turn-on voltage. This is one wherein a MOS structure is provided adjacent to the SCR and when the potential of the NW layer rises with a drain D as floating, a MOSFET breaks down precedently to increase the injection of a base current, thereby making it possible to set a breakdown voltage of the SCR low.
In order to improve the performance of the SCR as the protective element, the SCR needed to reduce the on resistance and adjust the turn-on voltage. To this end, the design of impurity profiles of the SCR is very important, and there was a need to repeat feedback from its post-fabrication characteristic to impurity profile design and an element size on several occasions.
The SCR is constituted of complex impurity profiles. In order to extract these impurity profiles, profile extracting TEGs each corresponding to a process for diffusing respective layers (ion implanting process) were fabricated and the respective TEGs cut off from a wafer were evaluated by a method based on Secondary Ion Mass Spectrometry (SIMS) or the like. The SCR shown in FIG. 7(a), for example, needed to fabricate six SIMS TEGs for the PD layer, NW layer, PW layer, ND layer, P+ layer and N+ layer.
A patent document, i.e., Japanese Unexamined Patent Publication No. Hei 6(1994)-53407 has described a protection circuit in which inverters and capacitors are used as triggers to operate an LVTSCR. A patent document, i.e., Japanese Unexamined Patent Publication No. Hei 9(1997)-181267 has described a circuit which protects a memory circuit from a negative ESD surge where the back of a substrate is not grounded. A patent document, i.e., Japanese Unexamined Patent Publication No. Hei 12(2000)-114521 has described a method for extracting an impurity profile from the characteristic of an actual element or device without using a TEG. A patent document, i.e., Japanese Unexamined Patent Publication No. Hei 13(2001)-339052 has described a method of accurately performing simulation of a protection circuit from an equivalent circuit in which an FET of an ESD protective element is substituted with a bipolar transistor.
However, the above methods involved several problems respectively. There is a need to first analyze the ESD protective element and the internal circuit in a set to evaluate ESD resistance. However, device or element structures contained in those include not only an SCR but also various types such as a MOSFET, a PN diode, etc. In order to determine the final impurity profiles of these element structures, the impurity profiles must be extracted with respect to their elements, thus taking a lot of trouble over it.
Since the SCR corresponding to one ESD protective element constitutes a complex impurity profile, it is difficult to estimate the impurity profile from the electric characteristic of the SCR. A problem arises in that when TEGs for evaluating impurity profiles are inserted, the number of the TEGs increases as described above and hence a TEG area becomes large, and each of the impurity profiles do not necessarily coincide with an impurity profile of an actual element or device.